1. Field of the Invention
Embodiments of the present invention relate to a computer, and more particularly, to a computer producing reduced noise during a power saving mode.
2. Description of the Related Art
ACPI (Advanced Configuration and Power Interface) is an open solution, generally implemented in computer hardware, operation systems, software, and peripheral device interfaces. This feature assists operating systems, hardware, and peripheral devices, e.g., those developed by Intel Inc., Microsoft, and Toshiba, to communicate with one another during power utilization.
In a conventional computer, the power management system operates according to a basic input/output system (BIOS), such that portions of the computer should implement a given non-operation period prior to disconnection from a power supply. A main object of the ACPI is to enable OS assisting Operating System Directed Power Management (OSPM) to manage all power activities, thereby providing the respective portions of the computer with power only when power is needed.
The ACPI, as announced in 1996, defines states C0, C1, C2, and C3 as power states of a CPU, with the C0 state being defined as a normal state, the C1 state being a halt state, the C2 state being a stop-grant state, and the C3 state being a stop clock state.
In the C2 state, the CPU performs a minimum level of activity, such as the snooping in order to keep a cache relationship. In the C3 state as the deep sleep mode, the CPU does not receive an external clock, so substantially all of the activities of the processor, except for a function to maintain data stored in a cache memory in the CPU, are not operational. Thus, in the C3 state deep sleep mode, less power is consumed compared to in the C2 state.
In recent years, Intel Inc. has developed Intel mobile voltage positioning II (IMVP II) in improved voltage regulation technology, such that a state C4 is introduced as a new power state of the CPU, being a deeper sleep mode than the C3 state deep sleep mode, and lowering a driving voltage when the CPU is not operating so as to reduce power dissipation.
FIG. 1 illustrates a computer with a conventional power supply system.
Referring to FIG. 1, a power supply module 140 provides a CPU 110 with driving power required to drive the CPU 110, i.e. a core voltage, converted from power supplied from an adapter or a battery, for example.
Here, the CPU 110 may have capabilities the same as or higher than Pentium Pro of Intel Inc., for example, and may require various levels of the core voltage (Vcore), depending on the type of CPU 110. The CPU 110 can provide the power supply module 140 with information about the Vcore level required through a voltage identification (VID) cord whose value range from 0 to 4 (VID [0, 4]), for example, and thereafter receive the Vcore having the required level.
In addition, the power supply module 140 can receive a state information signal including information of the driving mode of the CPU 110, provided from an input/output control hub, and may provide the Vcore to the CPU 110 with the corresponding level indicated in the state information signal. For example, when a state information signal, corresponding to the C4 state deeper sleep mode (DPRSLP), is received, a PWM control unit 150 in the power supply module 140 can control a power output unit 160 to provide the CPU 110 with a Vcore having a lower voltage level, e.g., 0.85V, than the voltage level for a normal state, which may be any value from 1.05V to 1.15V, for example.
Meanwhile, the power output unit 160 in the power supply module 140 can include various electric elements. For example, the power output unit 160 may include several ceramic capacitors, transistors for switching elements, inductors and the like.
However, in a conventional computer, when power is managed based on the driving state of the CPU 110, in order to perform power management, noise results from the power output unit 160, and in particular, noise is generated by the electric elements, e.g., ceramic capacitors and/or inductors, based on the change of the state information signal output from the input/output control hub. For example, upon the change of a logical value of a signal representing the deeper sleep mode is beyond several KHz, the generated noises resulting from the power output unit 160 are also beyond several KHz.
Furthermore, when a normal state power level is switched to a power saving mode, e.g., the deeper sleep mode, the voltage level of the Vcore will abruptly change. Such an abrupt change of voltage level may generate noise in the power output unit 160.